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| CY241V08A-12 Clock Generator with VCXO Features * * * * Integrated phase-locked loop (PLL) Low-jitter, high-accuracy outputs VCXO with analog adjust 3.3V operation Benefits * Highest-performance PLL tailored for multimedia applications * Meets critical timing requirements in complex system designs * Application compatibility for a wide variety of designs Frequency Table Part Number CY241V08A-12 Outputs 2 Input Frequency Range 27-MHz pullable crystal input per Cypress specification Output Frequencies One copy of 27 MHz One copy of 74.25 MHz VCXO Control Curve linear Block Diagram PLL OUTPUT DIVIDER 74.25MHz 27 XIN XOUT OSC XBUF/27MHz VCXO VDD VSS Pin Configuration CY241V08A-12 8-pin SOIC XIN VDD VCXO VSS 1 2 3 4 8 7 6 5 XOUT NC 74.25 MHz XBUF/27 MHz Cypress Semiconductor Corporation Document #: 38-07676 Rev. ** * 3901 North First Street * San Jose, CA 95134 * 408-943-2600 Revised June 02, 2004 CY241V08A-12 Pin Definitions Name XIN VDD VCXO VSS XBUF/27 MHz 74.25 MHz NC XOUT Pin Number 1 2 3 4 5 6 7 8 Reference crystal input. Voltage supply. Input analog control for VCXO. Ground. 27 MHz buffered crystal output. 74.25 MHz clock output. No Connect. Reference crystal output. Description Document #: 38-07676 Rev. ** Page 2 of 6 CY241V08A-12 Absolute Maximum Conditions Supply Voltage (VDD) ........................................-0.5 to +7.0V DC Input Voltage...................................... -0.5V to VDD + 0.5 Storage Temperature (Non-condensing)..... -55C to +125C Junction Temperature ................................ -40C to +125C Data Retention @ Tj = 125C................................> 10 years Package Power Dissipation...................................... 350 mW ESD (Human Body Model) JESD22-A114-B ............ > 2000V (Above which the useful life may be impaired. For user guidelines, not tested.) Pullable Crystal Specifications[1] Parameter FNOM CLNOM R1 R3/R1 DL F3SEPHI F3SEPLO C0 C0/C1 C1 Description Nominal crystal frequency Nominal load capacitance Equivalent series resistance (ESR) Ratio of third overtone mode ESR to fundamental mode ESR Crystal drive level Third overtone separation from 3*FNOM Third overtone separation from 3*FNOM Crystal shunt capacitance Ratio of shunt to motional capacitance Crystal motional capacitance Fundamental mode Ratio used because typical R1 values are much less than the maximum spec No external series resistor assumed High side Low side Comments Parallel resonance, fundamental mode, AT cut Min. Typ. - - - 3 150 300 - - 180 14.4 27 14 - - - - - - - 18 Max. - - 25 - - - -150 7 250 21.6 Unit MHz pF - W ppm ppm pF - fF Recommended Operating Conditions Parameter VDD TA CLOAD tPU Operating Voltage Ambient Temperature Max. Load Capacitance Power-up time for all VDD pins to reach minimum specified voltage (power ramps must be monotonic) Description Min. 3.135 0 - 0.05 Typ. 3.3 - - - Max. 3.465 70 15 500 Unit V C pF ms DC Electrical Specifications Parameter IOH IOL CIN VVCXO fXO [2] Name Output HIGH Current Output LOW Current Input Capacitance VCXO Input Range VCXO Pullability Range Supply Current Low Side High Side Description VOH = VDD - 0.5V, VDD = 3.3V VOL = 0.5V, VDD = 3.3V Except XIN, XOUT pins Min. 12 12 - 0 - 115 - Typ. 24 24 - - - - - Max. - - 7 VDD -115 - 40 Unit mA mA pF V ppm ppm mA IVDD AC Electrical Specifications (VDD = 3.3V) [3] Parameter[3] DC ER EF Name Output Duty Cycle Rising Edge Rate Falling Edge Rate Description Duty Cycle is defined in Figure 1, 50% of VDD Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF. See Figure 2. Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF. See Figure 2. Min. 45 0.8 0.8 Typ. 50 1.4 1.4 Max. 55 - - Unit % V/ns V/ns Notes: 1. Crystals that meet this specification includes: Ecliptek ECX-5808-27.000M 2. -115/+115 ppm assumes 2.5 pF of additional board level load capacitance. This range will be shifted down with more board capacitance or shifted up with less board capacitance. 3. Not 100% tested. Document #: 38-07676 Rev. ** Page 3 of 6 CY241V08A-12 AC Electrical Specifications (VDD = 3.3V) (continued)[3] Parameter[3] t9 t9 t9 t9 t10 Name Clock Jitter 74.25 MHz Clock Jitter XBUF/27 MHz Clock Jitter 74.25 MHz Clock Jitter XBUF/27 MHz PLL Lock Time Description Peak-to-peak period jitter Peak-to-peak period jitter 1000-cycle long term jitter 1000-cycle long term jitter Min. - - - - - Typ. 150 250 430 270 - Max. - - - - 3 Unit ps ps ps ps ms Test and Measurement Set-up VDD 0.1 F DUT Outputs CLOAD GND Voltage and Timing Definitions t1 t2 VDD 50% of VDD Clock Output 0V Figure 1. Duty Cycle Definition t3 t4 V DD 80% of V DD Clock Output 20% of V DD 0V Figure 2. ER = (0.6 x VDD) /t3, EF = (0.6 x VDD) /t4 Ordering Information Ordering Code CY241V8ASXC-12 CY241V8ASXC-12T Package Name SZ08 SZ08 Package Type 8-pin SOIC Operating Range Commercial Operating Voltage 3.3V 3.3V Features Linear VCXO control curve Linear VCXO control curve 8-pin SOIC - Tape and Reel Commercial Document #: 38-07676 Rev. ** Page 4 of 6 CY241V08A-12 Package Drawing and Dimensions 8-lead (150-Mil) SOIC S8 8 Lead (150 Mil) SOIC - S08 PIN 1 ID 4 1 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 3. REFERENCE JEDEC MS-012 0.230[5.842] 0.244[6.197] 0.150[3.810] 0.157[3.987] 4. PACKAGE WEIGHT 0.07gms PART # S08.15 STANDARD PKG. SZ08.15 LEAD FREE PKG. 5 8 0.189[4.800] 0.196[4.978] SEATING PLANE 0.010[0.254] 0.016[0.406] X 45 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0~8 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 51-85066-*C All product or company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07676 Rev. ** Page 5 of 6 (c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY241V08A-12 Document History Page Document Title: CY241V08A-12 Clock Generator with VCXO Document Number: 38-07676 REV. ** ECN NO. 230997 Issue Date See ECN Orig. of Change RGL New Data Sheet Description of Change Document #: 38-07676 Rev. ** Page 6 of 6 |
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